From an IRC chat with tear a while ago:
13:09 tear author of CPU-Z should be hanged by the balls
13:09 musky_work lol
13:09 tear for his visualization of SPDs
13:10 tear as it suggests that SPD contains number of per-frequency profiles
13:10 tear let me paste what I PM’d 4DoorGTZ
13:11 tear 4DoorGTZ: What I gather from info in pics from a review (http://www.xtremesystems.org/forums/showthread.php?241819-G.Skill-F3-12800CL7D-4GBECO-Reviewed-on-AMD) is that there is an xmp profile for 1600 and thats why they are listed as XMP ready cuz they’re sold as 1600 sticks not 1333. But no xmp profile for 1333, in pics on that link they have a few Jdec timing reading with the xmp 1600 in the cpu-z window.
13:11 tear tear: This is a common misconception. Profiles contain absolute values (e.g.
13:11 tear tCAS=10ns, which actually satisfies CL7 1333 and CL8 1600). It’s the way
13:11 tear CPU-Z presents the values that makes you think there are numerous,
13:11 tear per-frequency profiles (and that is not the case).
13:11 tear Your chips have (most likely) two profiles: JEDEC and XMP Profile 1 (XMP1).
13:12 tear —
13:13 tear so, expansion takes place in absolute units
13:14 tear that’s why frequency isn’t an “input” to the expansion process
13:14 tear SPD only contains this (in _slightly_ different format):
13:15 tear JEDEC stock(ns) tCL=11.25 tRCD=11.25 tRP=11.25 tRAS=35.00 tRC=46.25 tRFC=110.00
13:15 tear tRRD=6.00 tWR=15.00 tRTP=7.50 tFAW=30.00 tWTR=7.50
13:15 tear XMP1 stock(ns) tCL=7.50 tRCD=10.00 tRP=7.50 tRAS=30.00 tRC=42.50 tRFC=137.50
13:15 tear tRRD=7.50 tWR=12.50 tRTP=7.50 tFAW=37.50 tWTR=7.50
13:15 tear that’s it
13:15 tear there are no per-frequency timings as there’s no need for them
13:15 musky_work you could in theory have more than one XMP profile
13:15 tear yes, two.
13:16 musky_work ah
13:16 musky_work I have seen two
13:16 musky_work didn’t know that was the limit..
13:16 tear that is the limit
13:16 tear but point is, there’s no need for the per-frequency profiles
13:17 tear as the moment you know maximum values expressed in absolute units (nanoseconds, for instance)
13:17 tear you can always calculate the MEMCLK-expressed values
13:18 musky_work so actual timings are based on what your memclk is
13:18 tear by dividng time-in-nanoseconds by clock’s-cycle-time
13:18 tear exactly.
13:19 tear because on physical level
13:19 musky_work memclk increase = tighter actual timings?
13:19 tear (yes)
13:19 musky_work so if I buy PC 1333 CAS 7 memory
13:20 tear memory doesn’t care whether you tried to, say, issue a command 80 or 90 cycles
13:20 tear after end-of-refresh
13:20 tear you just can’t do that earlier than 137.5 ns
13:21 musky_work does that mean that based on the SPD settings and a memclk of 1333, I get an actual 7 ns on the first 4 settings (I foget which are which atm
13:21 tear 7 cycles
13:21 tear at 1333 (which has a MEMCLK of 666.6666, which corresponds to cycle time of 1.5ns)
13:21 musky_work cycles implies relative timing, correct?
13:22 tear yes.
13:22 musky_work so “CAS 7” is 7 cycles
13:22 tear yes
13:23 musky_work what is the formula?
13:23 tear it’s really simple —
13:23 musky_work for cycle time as a function of memclk
13:24 tear 1s / memclk
13:24 tear whereas memclk is actually half of DDR3 “standard”
13:24 musky_work yeah, I get that
13:24 tear (due to DDR)
13:24 tear 1/666.6666
13:24 tear .00150000015000001500
13:24 tear err.
13:24 tear my mistake
13:25 tear again!
13:25 tear 1s / memclk-in-Hz
13:25 tear ^^
13:25 tear 1/666666666
13:25 tear .00000000150000000150
13:25 musky_work other way
13:25 tear so it’s .00000000150000000150s
13:25 tear of course
13:25 musky_work 1/0.6666666666
13:25 tear it’s easier to use nanoseconds.
13:25 tear nope.
13:26 tear effectively yes
13:26 musky_work 1/0.6666666666 = 1.5
13:26 tear because you incorporated secons-to-nanosecond conversion
13:26 tear in the formula
13:26 musky_work lol
13:26 tear — either way
13:26 musky_work I would live to give myself that much credit
13:27 musky_work but, I actuall just tried to get a 1.5 result
13:27 tear that’s what I thought
13:27 tear the easiest to remember is probably
13:27 tear 10000/frequency-in-MHz
13:27 tear err
13:27 musky_work that is ns?
13:27 tear 1000 <- 13:27 musky_work or s 13:27 tear that is ns. 13:28 musky_work OK 13:28 tear 1000/666.6666 13:28 tear 1.50000015000001500000 13:28 tear ^^^^ 13:28 tear (for DDR3-13333) 13:28 musky_work 1600 = 1.25 ns cycle 13:28 tear yes 13:28 musky_work So if I bought 1600 CAS 7 memory 13:28 musky_work SPD should be.... 13:29 tear no higher than 7*1.25ns 13:29 musky_work 8.75 13:29 tear yes 13:29 tear and 8.75 / 1.5 (DDR3-1333) 13:29 musky_work that is what tpc -dram gives you? 13:29 tear (for instance) 13:29 musky_work the ns values? 13:29 tear 8.75/1.5 13:29 tear 5.83333333333333333333 13:29 tear is 5.83 cycles 13:30 tear which means you could run it CL6 at DDR3-1333 13:30 musky_work makes sense 13:30 tear nope, tpc -dram gives you cycles 13:30 musky_work I always knew that was about right 13:30 tear as memory controllers 13:30 musky_work just didn't know why... 13:30 tear don't know nanoseconds 13:30 tear physical side of timings prefers nanoseconds 13:31 tear but MCs prefer cycles (as everything is keyed off MEMCLK) 13:31 musky_work so I can read the # cycles the SPD is set for with tpc 13:32 tear almost, the *MC* is set for 13:32 tear tpc reads data actually programmed into the MC 13:32 tear by the BIOS 13:32 tear in other words -- TPC does not touch SPD 13:32 musky_work which is set by the memory module SPD on boot, right? 13:33 musky_work so you aren't reading it directly, which is fine 13:33 tear correct, but one needs to understand the difference 13:33 tear as application of SPD data is a dynamic process 13:33 musky_work and that is what you guys are messing with now 13:34 tear obviously, same SPD will yield different MC configurations depending on timing 13:34 musky_work yeah 13:34 musky_work but 13:34 musky_work you really only have what? 3 available on a normal G34 server board 13:34 musky_work ? 13:35 musky_work so you can boot at memclk of 800, 1066, or 1333 13:35 tear 400 533 or 667, technically 13:35 musky_work cycle isn't going to change 13:35 tear it's not, unless you OC! 13:35 musky_work regardless of memclk 13:35 tear as bumping refclk affects memclk 13:36 musky_work still 13:36 musky_work cycle is not going to change 13:36 musky_work actual timing will 13:36 musky_work based on memclk 13:36 musky_work which will be affected by refclk 13:36 tear if by "cycle" you mean configuration stored in the MC 13:36 tear then yes, the MC configuration, once applied at boot 13:36 tear does not change 13:36 musky_work I mean the "7" in CAS 7 rating 13:36 tear yes. 13:36 tear that doesn't change 13:37 tear but effective timing does (due to cycle time adjustment) 13:37 tear === 13:37 tear but 13:37 tear just so we're clear 13:38 tear BIOS will always try to apply best timings given the MEMCLK 13:39 musky_work yeah, that makes sense 13:39 musky_work bios applie stiming based on how it sets memclk 13:39 tear yes 13:40 musky_work wow...I actually learned something today... 13:40 tear 13:40 tear you're welcome 13:40 musky_work thank you 13:40 tear and just to illustrate what we learned: 13:41 tear following data come from _single_ profile (JEDEC) 13:41 tear $ ./d3sak -tjS gskill-f3-12800cl6-2gbxh-stock.bin 13:41 tear d3sak: DDR3 Swiss Army Knife 13:41 tear d3sak comes with ABSOLUTELY NO WARRANTY; for details 13:41 tear see `COPYING' file located in source directory 13:41 tear Read 256 bytes 13:41 tear SPD checksum: 5a 6e 13:41 tear SPD checksum (calculated): 5a 6e 13:41 tear SPD checksum is correct! 13:41 tear Module: F3-12800CL6-2GBXH 13:41 tear JEDEC MTB: 0.1250ns 13:41 tear JEDEC tCKmin: 1.25ns (DDR3-1600) 13:41 tear JEDEC Supported CAS latencies: CL7 CL8 CL9 13:41 tear JEDEC stock(ns) tCL=11.25 tRCD=11.25 tRP=11.25 tRAS=35.00 tRC=46.25 tRFC=110.00 13:41 tear tRRD=6.00 tWR=15.00 tRTP=7.50 tFAW=30.00 tWTR=7.50 13:41 tear JEDEC stock(MTB) tCL=0x5A tRCD=0x5A tRP=0x5A tRAS=0x118 tRC=0x172 tRFC=0x370 13:41 tear tRRD=0x30 tWR=0x78 tRTP=0x3C tFAW=0xF0 tWTR=0x3C 13:41 tear JEDEC DDR3-1067 tCL=6.00 tRCD=6.00 tRP=6.00 tRAS=18.67 tRC=24.67 tRFC=58.67 13:41 tear tRRD=3.20 tWR=8.00 tRTP=4.00 tFAW=16.00 tWTR=4.00 13:41 tear JEDEC DDR3-1333 tCL=7.50 tRCD=7.50 tRP=7.50 tRAS=23.33 tRC=30.83 tRFC=73.33 13:41 tear tRRD=4.00 tWR=10.00 tRTP=5.00 tFAW=20.00 tWTR=5.00 13:41 tear JEDEC DDR3-1600 tCL=9.00 tRCD=9.00 tRP=9.00 tRAS=28.00 tRC=37.00 tRFC=88.00 13:41 tear tRRD=4.80 tWR=12.00 tRTP=6.00 tFAW=24.00 tWTR=6.00 13:42 tear (ignore MTB, that's for next lesson) 13:42 musky_work lol 13:42 tear but if you look at (ns) values you'll see they correspond to MEMCLK-expressed values 13:42 musky_work so when i go into the bios of a normal single proc board and can adjust tCL for example 13:43 musky_work what am I setting? 13:43 musky_work I think that is where everyone get confused 13:43 tear you're setting MEMCLK-based value 13:43 musky_work ahh 13:43 tear absolute values are only in the SPD 13:44 musky_work so I set memory to 1600 and set tCL to 8, that is 8 ns for the memory speed on 1600(800 DDR) 13:44 tear that is 8*1.25ns 13:44 tear 8 cycles * 1.25ns/cycle 13:44 tear == 10ns 13:45 musky_work so I am not setting ns 13:45 musky_work actual ratio 13:45 tear 20:45 <@musky_work> so I am not setting ns
13:45 tear that is correct
13:45 musky_work *actually setting cycles
13:45 tear only spot where absolute (ns) values are is SPD
13:46 musky_work so I am not actually setting memclk-specific anything in the bios
13:46 tear other than memclk itself.
13:46 musky_work I am setting the memclk, and I am setting the timing cycles
13:47 tear yes, combination of both happens on the wires.
13:47 musky_work If a change memclk, I don’t automatically change cycles
13:47 musky_work I do change actual timing in ns
13:47 tear nope. but you do change the wires
13:47 tear yes.
13:47 tear exaclty.
13:47 tear *exactly.
13:47 musky_work got it
13:48 musky_work that explains a lot actually
13:48 tear as I said, by the balls…
13:48 musky_work and was not what i thought it did
13:49 musky_work yeah, I’ll confess, I assumed SPD was multiple values
13:49 musky_work because I think that any time I have seen it, it was shown that way
13:49 tear that’s right
20:09 <&tear> author of CPU-Z should be hanged by the balls
Topic set by tear on Fri Nov 25 2011 13:50:31 GMT-0600 (Central Standard Time)
13:50 musky_work and it sort of is, in practical terms – each memclk has a different # cycles
13:51 tear yes
13:51 musky_work SPD is a single value, effect “CAS timings” change based on memclk
13:51 tear yes
13:52 musky_work and every place you look, from your memory packaging to the bios, is showing you cycles
13:52 tear yes.
13:52 musky_work I need to write this down…don’t boot me from the channel…
13:52 tear but remember that both marketed memory specs and BIOS also include the frequency
13:53 tear CL7 is meaningless unless coupled with frequency
13:53 musky_work marked memory spec, yes
13:53 firedfly_laptop “/kick musky_work”
13:53 musky_work bios, not necessarily
13:53 musky_work I’ll explain
13:53 musky_work memclk and CAS timings are separate settings
13:54 musky_work so I can set timings to CAS 8 and change memclk from 1333 to 1600
13:55 musky_work what you end up with is different actual timings, but both “CAS 8”
13:55 tear (yes)
13:55 musky_work memory packaging, yes – memclk is not adjustable..
13:56 musky_work SPD is set such that you end up with 8 cycles at 1600 MHz
13:57 musky_work you should teach a class
13:57 tear I just did!
13:57 musky_work yeah, but to one student…
13:57 musky_work and he is useless…I know the guy…
13:57 tear — teach a man how to teach a man how to fish.
13:58 musky_work lol
13:58 musky_work teach a man how to teach a man how to fish, and people stop bothering you for fishing advise…
13:58 tear I’m happy you enjoyed the lesson